There is increasing interest in the use of carbon nanotubes in electronic circuits, and in particular logic cells that are configured to perform inverting functions and any number of Boolean logic functions. An ideal carbon nanotube logic-based circuit can have significantly less fan-out-of-four (FO4) delay and significantly lower energy requirements than a conventional complementary metal oxide semiconductor (CMOS)-based circuit. Unfortunately, the current state of carbon nanotube manufacture results in a significant percentage of misaligned carbon nanotubes. A misaligned carbon nanotube can result in a short between contacts of a logic cell, or the inadvertent creation of an incorrect logic function. Because of the high misalignment rates, discarding defective chips with misaligned carbon nanotubes or reconfiguring around defective logic cells via testing may be very expensive. Traditional fault tolerance techniques, such as Triple Modular Redundancy (TMR), are expensive and may not be adequate for such high defect rates. Thus, there is a need for a circuit design that is not impacted, or is otherwise immune, to misaligned carbon nanotubes, and a verification methodology for determining whether an existing circuit design is immune to misaligned carbon nanotubes.